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FIR Filter를 이용하는 디지털 위상 고정 루프와 저전력 밴드갭 기준 전압 회로 연구

Title
FIR Filter를 이용하는 디지털 위상 고정 루프와 저전력 밴드갭 기준 전압 회로 연구
Authors
이종미
Date Issued
2015
Publisher
포항공과대학교
Abstract
This thesis describes an in-band noise filtering 32-tap FIR-embedded fractional-N digital PLL and a 29nW bandgap reference circuit. Firstly, a 1.9-GHz digital ΔΣ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression is proposed. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region. Secondly, a low-power bandgap voltage reference circuit with a leakage-based two-diode PTAT generation is proposed. With no need of start-up circuit, the fabricated in 0.35μm CMOS consumes only 29nW from 1.4V supply at the room temperature. Measurements show a temperature coefficient of 12.75ppm/℃ and a line regulation of 0.198%/V.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001914616
https://oasis.postech.ac.kr/handle/2014.oak/93174
Article Type
Thesis
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