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A Dual-loop CMOS PLL with the Max-to-min Frequency Ratio Larger than Five Guaranteed under PVT Corners

Title
A Dual-loop CMOS PLL with the Max-to-min Frequency Ratio Larger than Five Guaranteed under PVT Corners
Authors
박홍준
POSTECH Authors
박홍준
Publisher
IT-SoC
URI
http://oasis.postech.ac.kr/handle/2014.oak/87127
Article Type
Conference
Citation
International SoC Design Conference, page. 313 - 316
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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