Open Access System for Information Sharing

Login Library

 

Conference
Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling

Title
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling
Authors
심재윤성기환김병섭임지훈박홍준
Date Issued
2014-05-17
Publisher
대한전자공학회
URI
https://oasis.postech.ac.kr/handle/2014.oak/67934
Article Type
Conference
Citation
대한전자공학회 SoC 학술대회, 2014-05-17
Files in This Item:
There are no files associated with this item.

qr_code

  • mendeley

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher

김병섭KIM, BYUNGSUB
Dept of Electrical Enginrg
Read more

Views & Downloads

Browse