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Verilog Synthesis of USB 2.0 Full-speed Device PHY IP
- Title
- Verilog Synthesis of USB 2.0 Full-speed Device PHY IP
- Date Issued
- 2013-11-18
- Publisher
- IEIE & IEEE, Int. SoC Design Conference(ISOCC)
- Article Type
- Conference
- Citation
- IEIE & IEEE, Int. SoC Design Conference(ISOCC), 2013-11-18
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Related Researcher
- 박홍준PARK, HONG JUNE
- Dept of Electrical Enginrg