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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 정윤하 | - |
| dc.date.accessioned | 2018-06-18T04:57:30Z | - |
| dc.date.available | 2018-06-18T04:57:30Z | - |
| dc.date.created | 2012-04-27 | - |
| dc.date.issued | 2011-09-29 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/61503 | - |
| dc.publisher | The Japan Society of Applied Physics | - |
| dc.relation.isPartOf | 2011 International Conference on Solid State and Device Materials | - |
| dc.title | Analysis of Bottom Channel Effect in Silicon Nanowire FET based on Bulk-Silicon: Reduction of Parasitic Capacitance caused by SiGe layer | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | 2011 International Conference on Solid State and Device Materials | - |
| dc.citation.conferenceDate | 2011-09-28 | - |
| dc.citation.conferencePlace | JA | - |
| dc.citation.title | 2011 International Conference on Solid State and Device Materials | - |
| dc.contributor.affiliatedAuthor | 정윤하 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 정윤하JEONG, YOON HA
- Dept of Electrical Enginrg