HDP/SOG STI로부터 발생한 STRAIN이 RECESS CHANNEL ARRAY TRANSISTOR 구조 DRAM의 DATA RETENTION TIME에 미치는 특성 평가

Abstract

The data retention time characteristics of recess channel array transistor (RCAT) structure DRAM stressed by shallow trench isolation (STI) has been investigated. The structure of RCAT is explained, and inducement of mechanical stress and its effects are clarified. Spin on glass (SOG) STI induces tensile stress but high density plasma - chemical vapor deposition (HDP-CVD) STI induces compressive stress. Because of these characteristics, hybrid STI which uses both HDP-CVD and SOG induces different stress at a different position of RCAT.Measurement of junction leakage current, threshold voltage and subthreshold current indicate that tensile stress is induced at channel region. The differences of gate induced drain leakage (GIDL) current indicate that the drain region is subject to compressive stress. Accordingly both HDP-CVD and SOG region determine the data retention time. For the experimental wafer, GIDL current is used to calculate compressive stress. The result shows that the distribution of compressive stress agrees well with the distribution of the data retention time.