공정 변이를 고려한 초집적 회로의 확률 통계적 누설 전류 최소화

Abstract

Aggressive technology scaling makes the process variations a significant problem in VLSI designs. Process variation causes device property fluctuation and leads to undesirable circuit performance variation. Large circuit performance variation may induce serious yield loss problem, process variation should be considered in model VLSI design. Especially, leakage current is known to extremely sensitive to process variation. The leakage power of a circuit rapidly increases as the technology scales down. In recent technology, the leakage power has been a significant contributor to the total power consumption of a circuit.Well-known traditional method considering the variation of circuit performance is the worst-case corner-based design, which estimates the performance of a circuit by assuming that process parameters of the circuit have worst-case values. Unfortunately, this approach is too pessimistic for recent technology with small feature sizes.Statistical design, which analytically evaluates a circuit’s performance variation and designs a circuit based on the statistical circuit information, is a new and promising technique for variation-aware design in the deep-sub-micron (DSM) era. Many studies have been conducted on the statistical analysis of a circuit, and recent techniques show satisfactory accuracy and efficiency. However, unlike the statistical analysis techniques, study on the practical statistical optimization method is still in its infancy. Since statistical design handles many circuit parameters as random variables, statistical design has different characteristics from those of the traditional deterministic design. For this reason, new analysis and optimization methods different from the deterministic design techniques are required for statistical design. This dissertation proposes a novel statistical leakage minimization method and useful analysis index for statistical optimization. This dissertation proposes the use of a new statistical index for statistical optimization: the timing yield slack (yield slack). Timing yield slack is statistical counterpart of the timing slack in deterministic design. Like timing slack in deterministic optimization, timing yield slack is an index that represents the excess timing resource available in a gate or a circuit. Timing yield slack is used to as an efficient criterion for determining the timing yield violation during the statistical optimization. To define the yield slack of the gate, this paper will define the timing yield and required timing yield of a gate and propose their efficient calculation methods. Furthermore, this dissertation also proposes effective statistical leakage minimization method based on timing yield slack. This dissertation analyzes the differences on the timing characteristics between statistical optimization and traditional deterministic optimization and also proposes an effective strategy for using the timing resources of a circuit for effective statistical optimization. Proposed leakage minimization method uses dual-Vth technique to reduce leakage current. Proposed minimization algorithm hierarchically finds the replacement candidate for leakage minimization. Proposed algorithm uses efficient criterion that has low computational complexity to screen out gates that are not suitable for replacement. Then, proposed algorithm uses accurate criterion to find replace candidate. This hierarchical selection improves optimization speed by reducing search time of the accurate criterion. In experiments using the ISCAS-85 benchmarks, leakage minimizations performed with decreasing timing yield of circuits from 99.87% to 99%. In the experiments, the proposed efficient algorithm reduces the 99-percentile of the circuit leakage current by 26% of original leakage current on average, which is 25.2% of additional reduction, compared with existing statistical leakage minimization method did. In efficiency, the proposed efficient algorithm showed 18.45% of runtime improvement than that of the existing method on average.