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Stacked Gate Flash EEPROM에서 Bit Line Vpltage Stress가 Floating Gate의 Charge Loss에 미치는 영향 연구

Title
Stacked Gate Flash EEPROM에서 Bit Line Vpltage Stress가 Floating Gate의 Charge Loss에 미치는 영향 연구
Authors
안병희
Date Issued
2000
Publisher
포항공과대학교
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001905124
http://oasis.postech.ac.kr/handle/2014.oak/5353
Article Type
Thesis
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