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dc.contributor.author심재윤ko
dc.contributor.author박승진ko
dc.contributor.author하현수ko
dc.contributor.author서윤재ko
dc.contributor.author박홍준ko
dc.date.accessioned2018-06-15T06:20:23Z-
dc.date.available2018-06-15T06:20:23Z-
dc.date.created2009-03-23-
dc.date.issued2008-11-04-
dc.identifier.citationIEEE Asian Solid-State Circuits Conference-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/51123-
dc.publisherIEEE-
dc.titleA Transister-Based Background Self-Calibration for Reducing PVT Sensitivity with Design Example of an Adaptive Bandwidth PLL-
dc.typeConference-
dc.type.rimsCONF-
dc.contributor.localauthor심재윤-
dc.contributor.localauthor박홍준-
dc.citation.titleIEEE Asian Solid-State Circuits Conference-
dc.description.journalClass1-
dc.identifier.conferencecountryJA-

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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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