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Showing results 161 to 180 of 5036

Issue Date	Title
2015-Jun	A 35dB-Linear Variable Gain Amplifier Circuit of Digital-Beamformer for Ultrasound Medical Imaging ITC-CSCC 2015, 2015-06-29 박홍준; 조성은; 김병섭; 심재윤
2015-Jun	A 35dB-Linear Variable Gain Amplifier Circuit of Digital-Beamformer for Ultrasound Medical Imaging ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications, 2015-06-29 심재윤; 조성은; 김병섭; 박홍준
2013-Jan	A 3Gb/s 2.09mm2 100b error-correcting BCH decoder in 0.13um CMOS process IEEE ASP-DAC 2013, 2013-01-23 LEE, YOUNGJOO; YOO, HOYOUNG; PARK, IN-CHEOL
2005-Feb	A 3Gb/s 8b Single-Ended Transceiver for 4-drop DRAM Interface with Digital Calibration of Equalization, Skew and Offset Coefficients IEEE International Solid State Circuit Conference, page. 520 - 521, 2005-02-01 박홍준
2001-Feb	A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture International Solid-State Circuit Conference, page. 378 - 379, 2001-02-07 심재윤
2004-Oct	A 4-Gb/s Single-Ended Transmitter for DRAM Interface with Pre-Emphasis and Low Skew Multiplexing using a 0.25um CMOS Process International SoC Design Conference, page. 514 - 517, 2004-10-01 박홍준
2013-Feb	A 416-kS/s 12-bit algorithmic ADC compensating capacitance mismatch of MDAC in digital domain International Conference of Electronics, Information and Communication, 2013-02-01 심재윤; 박홍준; 엄지용; 이재승; 여동희; 이상수; 이경곤
2013-Jan	A 416-kS/s 12-bit Algorithmic ADC Compensating Capacitance Mismatch of MDAC in Digital Domain IEIE & IEEE, ICEIC, 2013-01-30 박홍준; 엄지용; 이재승; 여동희; 이상수; 이경곤; 심재윤
2009-Jun	A 45/46/34% PAE linear polar transmitter for EDGE/WCDMA/Mobile-WiMax IEEE MTT-S Int. Microw. Sympo, 2009-06-07 김범만; Jinsung Choi; Dongsu Kim; Daehyun Kang; Myoungsu Jun; Boshi Jin; Jungmin Park
2008-Feb	A 480MHz 5-phase digital DLL using current controlled delay line 제 15회 반도체 학술 대회, 2008-02-20 박홍준; 전성환; 박상훈; 최광희; 심재윤
2008-Feb	A 480MHz 5-phase digital DLL using current controlled delay line 제15회 한국반도체학술대회, page. 743 - 744, 2008-02-22 심재윤; 전성환; 박상훈; 최광희; 박홍준
2009-Feb	A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS Technology International Solid-State Circuits Conference, 2009-02-09 김병섭; Vladimir Stojanovi
2008-Nov	A 4Gbps 3-bit parallel Transmitter with the Crosstalk-Induced Jitter Compensation using TX Data Timing Control IEEE Asian Solid-State Circuits Conference, 2008-11-04 심재윤; 정해강; 박홍준
-	A 4Gbps 3-bit parallel Transmitter with the Crosstalk-Induced Jitter Compensation using TX Data Timing Control IEEE Asian Solid-State Circuits Conference 박홍준
2009-Nov	A 5-7 Gbps Peak Detector for Serial-Link International SoC Design Conference, 2009-11-23 심재윤; 김종훈; 신정범; 박홍준
2009-Nov	A 5-7 Gbps Peak Detector for Serial-Link International SoC Design Conference, 2009-11-23 박홍준; 김종훈; 신정범; 심재윤
2014-Feb	A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface IEEE International Solid-State Circuits Conference, page. 48 - 49, 2014-02-10 심재윤; 백동훈; 김병섭; 박홍준
2014-Feb	A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface IEEE International Solid-State Circuits Conference(ISSCC), 2014-02-10 박홍준; 백동훈; 김병섭; 심재윤
2014-Feb	A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface International Solid-State Circuits Conference, 2014-02-11 김병섭; 백동훈; 박홍준; 심재윤
2014-Sep	A 5.67mW 9Gb/s DLL-Based Reference-less CDR with Pattern-Dependent Clock-Embedded Signaling for Intra-Panel Interface IEEE International Solid-State Circuits Conference(ISSCC), 2014-09-16 박홍준; 백동훈; 김병섭; 심재윤

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