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Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors SCIE SCOPUS

Title
Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors
Authors
Liu, WLiou, JJChung, AJeong, YHChen, WCLin, HC
Date Issued
2009-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGI
Abstract
Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and ON-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.
URI
https://oasis.postech.ac.kr/handle/2014.oak/31027
DOI
10.1109/LED.2009.2025610
ISSN
0741-3106
Article Type
Article
Citation
IEEE ELECTRON DEVICE LETTERS, vol. 30, no. 9, page. 969 - 971, 2009-09
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정윤하JEONG, YOON HA
Dept of Electrical Enginrg
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