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A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface SCIE SCOPUS

Title
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface
Authors
Lee, SKPark, SJPark, HJSim, JY
Date Issued
2011-03
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
This paper presents a 100 kS/s, 1.3 mu W, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 mu m CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 mu W at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 fJ/conversion-step.
URI
https://oasis.postech.ac.kr/handle/2014.oak/24969
DOI
10.1109/JSSC.2010.2102590
ISSN
0018-9200
Article Type
Article
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 46, no. 3, page. 651 - 659, 2011-03
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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