A RX Adaptive Equalizer and a TX Power Reduction Scheme for 5Gbps Differential Serial Link Transceiver

Abstract

In this thesis, a RX adaptive equalizer and a power reduction scheme in a differential serial link transceiver are proposed.Firstly, an adaptive equalization scheme based on all-digital jitter measurement is proposed for CTLE preceding CDR in a receiver circuit for high-speed serial interface. Two jitter clocks generated by receiver CDR are used for the jitter measurement. The optimum equalization coefficient of CTLE is determined automatically during the initial training operation based on the measured jitter. The proposed circuit finds the optimum equalization coefficient of CTLE for 20”, 30”, 40” FR4 channels at the data rate of 5Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13μm process. The equalizer consumes 12mW at 1.2V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.Secondly, by increasing the termination resistance to 4•ZO at both TX and RX of a differential serial link with a CML driver, the transceiver power is reduced by 37%. The TX power is reduced by 54%. The TX includes a CML driver, a pre-driver and a serializer. While the reflection and the ISI are increased due to the increase of the termination resistance, they are compensated for by a 2-tap DFE circuit at RX. The DFE tap position for reflection and the DFE coefficients for ISI and reflection are found automatically during the initial training mode. The transceiver chip fabricated in a 0.13μm process shows a BER<1E-12 with 25, 30 and 35cm FR4 channels at 5Gbps.