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A Study on Fabrication and Electrical Characterization of Junctionless Silicon Nanowire FETs

A Study on Fabrication and Electrical Characterization of Junctionless Silicon Nanowire FETs
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This study deals with fabrication and electrical characterization of junctionless silicon nanowire field effect transistors (Si-JNTs) which regarding as next-generation semiconductor devices. The Si-JNT is a transistor removing junctions which conventional inversion-mode device has by implanting same type of dopants to source, channel and drain at high concentration. Therefore, the fabrication process is simpler and the fabrication cost is much lower than the inversion-mode devices because the Si-JNT does not need to consider the impurity diffusion problem in the process of device ion implantation and dopant activation annealing. Recently, the characterization of the Si-JNT has been performed by several groups
however it is limited to the evaluation of devices with long channel length. To evaluate the possibility of utilizing the Si-JNT as the next-generation devices, characterization of Si-JNT having short channel length is very important. Therefore, in this study, the following works have been performed. First, to evaluate the performance of devices with short channel, fabrication of n-channel Si-JNT with gate lengths in the range of 20-250 nm has been demonstrated, and has compared their electrical performances with conventional inversion-mode silicon nanowire transistors (Si-INTs). The junctionless tri-gate silicon transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion / Ioff ratio (> 106), good subthreshold slope (~79 mV/dec), and low drain-induced barrier lowering (~ 10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the Si-JNT a promising candidate for sub 22-nm technology nodes. Second, The DC performance and low frequency (LF) noise behaviors after hot carrier (HC) induced stress are compared for Si-JNTs and Si-INTs to assess the reliability of the devices. Less DC degradation is found in the Si-JNT than in the Si-INT. Due to the low lateral peak electric field (E-field) and electrons traveling through the center of the nanowire, the LF noise increment after HC induced stress in the Si-JNT is much lower than in the Si-INT. Furthermore, due to the higher lateral peak E-field located under the gate and the conduction path that occurs near the surface, the LF noise of the Si-INT is very sensitive to HC stress. The LF noise characteristic of the Si-JNT leads to reduced signal-to-noise ratios, and therefore, it is considered to be a promising candidate for sensors with ultrahigh sensitivity. Finally, the extraction of series resistances using Y-function technique from fabricated n-channel Si-JNTs and Si-INTs has been demonstrated. As the channel length is scaled down, channel resistance is gradually decreased and it has therefore become a key issue to keep the value of series resistance smaller than channel resistance to ensure the device performance. Due to this reason, therefore, it is important to extract the series resistance and to examine its behavior in terms of appropriate device parameters and the complexity of contact configuration. The extracted values of series resistance are nearly constant versus gate voltage as expected ohmic contacts in the devices. However, both devices show fluctuation of series resistance for all gate length. This indicates that the careful optimization is needed about complicated contact geometry between source/drain and channel from device to device. With the gate length of 250 nm, the averaged series resistance of 2.1 k and 3.5 k has been obtained for the Si-JNTs and Si-INTs, respectively. The lower series resistance in Si-JNT devices could be attributed to have no gradient of the doping concentration between the source/drain and channel.
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