CMOS digital duty cycle correction circuit for multi-phase clock

Abstract

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50 +/- 0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 mum CMOS technology is used in this work.