High-k/Metal Gate FETs의 전기적 특성분석에 대한 연구

Abstract

With scaling-down of CMOS technology, problems such as an exponential increase of gate leakage current, velocity saturation, electrostatics degradation, and power consumption have been an obstacle to further scale the devices. High-k/metal gate stacks were introduced to overcome the traditional scaling limitation and reduce gate leakage on future technologies. Subsequently, the new material-based FETs and advanced structures have been successfully implemented in manufacturing fab as well as laboratory, and have been investigated due to the advantages for high performance, high speed, and low power applications. Although many researchers have made a greater effort to extensively study the characteristics, many problems still remain unsolved. In this study, hot carrier effect in high-k/metal gate MOSFETs is characterized using RF small-signal parameter analysis. A modified surface channel resistance model is proposed to explain a novel hot carrier degradation of RF small-signal parameters. The versatile model can be applied to not only conventional SiO2/poly-Si gate MOSFETs, but also high-k/metal gate nMOSFETs. RF performances and hot carrier effects of MOSFETs at cryogenic temperature is investigated. RF performances of high-k/metal gate MOSFET at 77 K are improved more than those of SiO2/poly-Si gate MOSFET although DC performances are improved similarly. The high-k MOSFET with 100 nm gate length achieves 127.4 GHz fT (current gain cut-off frequency) and 75.4 GHz fmax (maximum oscillation frequency) at 77 K. Under hot carrier injection, gm of high-k nMOSFET at 77 K is degraded more than that at 300 K although Vth shift is less. The cause of gm reduction is discussed related to the charge trapping. Continued success in scaling MOSFETs has increased the feasibility of their operation in the quasi-ballistic regime. Quasi-ballistic transport in nanoscale high-k/metal gate MOSFETs is studied based on RF S-parameter analysis. RF S-parameter-based a simple experimental methodology is used for direct extraction of device parameters (Leff, RSD, Cinv) and the effective carrier velocity (veff) from the targeted short channel devices. Furthermore, an analytical top-of-the-barrier model which self-consistently solves the Schrödinger-Poisson equations is used to determine the ballistic carrier velocity (vinj) at the top of the barrier near the source. Based on the results of the experimental extraction and analytical calculations, the backscattering coefficient (rsat) and ballistic ratio (BRsat) are calculated to assess the degree of the transport ballisticity for the nMOSFETs. It is found that the conventional high-k/metal gate nMOSFETs will approach a ballistic limit at an effective gate length (Leff) of approximately 7 nm. The efforts to overcome the limitation of planar MOSFETs have been implemented by adopting novel structure, new material, and stress engineering on devices. Among them, FinFET as a promising device showed great potential due to excellent electrostatics, scalability, and manufacturability for nanoscale CMOS. The effect of the surface orientation and channel direction on FinFET performance is analyzed experimentally by comparing the characteristics of (100)/<100> FinFETs and (110)/<110> FinFETs. The current and transconductance of (100)/<100> FinFETs are greater than those of (110)/<110> FinFETs, which is attributed to the relatively lighter transport effective mass (mt) of (100)/<100> FinFETs. In the ballistic transport regime beyond drift-diffusion, an effect of the different orientation/direction is further demonstrated and provides deeper insight into its intrinsic impact as well as its validity. Furthermore, an abnormal behavior—that the difference of the effective carrier velocity (veff) and the electron mobility (μeff) between the (100) and (110) orientations decreases with scale-down—is investigated using scattering mechanisms.