DC Field | Value | Language |
---|---|---|
dc.contributor.author | 이선규 | en_US |
dc.date.accessioned | 2014-12-01T11:48:14Z | - |
dc.date.available | 2014-12-01T11:48:14Z | - |
dc.date.issued | 2012 | en_US |
dc.identifier.other | OAK-2014-01114 | en_US |
dc.identifier.uri | http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001386092 | en_US |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/1616 | - |
dc.description | Doctor | en_US |
dc.description.abstract | In this thesis, a 650Mb/s-to-8Gb/s locking referenceless CDR circuit with automatic frequency acquisition and 1.25ps resolution sub-exponent TDC are proposed with an all-digital PLL with the TDC as a design example.Firstly, a 650Mb/s-to-8Gb/s referenceless CDR circuit is proposed with an automatic tracking of data-rate. For efficient frequency acquisition, a DLL-based loop is used with a simple phase/frequency detector. The CDR, implemented in a 65nm CMOS, shows a BER of less than 10-12 with the best performance in lock-range, power consumption, and size compared with previously reported continuous-rate CDRs.Secondly, an all-digital PLL for clock generation of wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2x time amplifiers, the TDC efficiently generates the exponent-only information for fractional time difference. To improve linearity in a wide input range, a replica-based self-calibration scheme is applied to the time amplifier. The TDC, implemented in a 0.18 m CMOS, shows the minimum resolution of 1.25 ps with a total conversion range of 2.5ns, the maximum operating frequency of 250MHz, and power consumption of 1.8mW at 60MHz. The measured rms jitter of PLL was 5.03 ps at 960 MHz. | en_US |
dc.language | eng | en_US |
dc.publisher | 포항공과대학교 | en_US |
dc.rights | BY_NC_ND | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
dc.title | A 650Mb/s-to-8Gb/s Referenceless CDR with Automatic Acquisition of Data Rate and a 1.25 ps Resolution Sub-Exponent TDC for All-Digital PLL | en_US |
dc.title.alternative | 650 Mb/s - 8 Gb/s의 데이터속도를 자동으로 추적하는 클락 및 데이터 복원회로 및 All-Digital PLL의 사용에 적합한 1.25 ps의 해상도를 갖는 Sub-Exponent방식의 시간-디지털 변환회로 | en_US |
dc.type | Thesis | en_US |
dc.contributor.college | 일반대학원 전자전기공학과 | en_US |
dc.date.degree | 2012- 8 | en_US |
dc.contributor.department | 포항공과대학교 | en_US |
dc.type.docType | Thesis | - |
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