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dc.contributor.author성기환en_US
dc.date.accessioned2014-12-01T11:47:17Z-
dc.date.available2014-12-01T11:47:17Z-
dc.date.issued2011en_US
dc.identifier.otherOAK-2014-00595en_US
dc.identifier.urihttp://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000900598en_US
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/1097-
dc.descriptionMasteren_US
dc.description.abstractThis research implements USB 2.0 Serial Interface Engine (SIE) using Verilog. The implemented SIE consists of packet disassembly, protocol engine and packet assembly. The implemented SIE verifies the correct operation using input pattern of IN/OUT Transaction, thereby checking Token, Data, Handshake packet identification, Data packet Generation, Handshake packet Generation, CRC checking and Generation. The SIE is implemented on Xilinx Virtex-5 FPGA chip and uses 8775 gates. To behavioral simulate, NC-verilog simulator is used. To synthesis and post simulate, ISE software program is used.en_US
dc.languagekoren_US
dc.publisher포항공과대학교en_US
dc.rightsBY_NC_NDen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/2.0/kren_US
dc.titleFPGA Implementation of USB 2.0 Serail Interface Engine Chip Using Verilogen_US
dc.typeThesisen_US
dc.contributor.college일반대학원 전자전기공학부en_US
dc.date.degree2011- 2en_US
dc.contributor.departmentPOSTECHen_US
dc.type.docTypeThesis-

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