Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory
SCIE
SCOPUS
- Title
- Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory
- Authors
- KIM, HYANGWOO; CHO, CHOHYEONSU; KWAK, HYEONTAK; SEO, MYUNGHAE; LEE, SEUNGHO; KONG, BYOUNG DON; BAEK, CHANG KI
- Date Issued
- 2022-01
- Publisher
- Springer Verlag
- Abstract
- Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode-cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of - 0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/109586
- DOI
- 10.1186/s11671-022-03667-7
- ISSN
- 1931-7573
- Article Type
- Article
- Citation
- Nanoscale Research Letters, vol. 17, no. 28, 2022-01
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- There are no files associated with this item.
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