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Browsing by  AuthorJi-Hoon Lim

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Showing results 1 to 4 of 4
Article
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMsSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, vol. 63, no. 2, page. 141 - 145, 2016-02

Article
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM InterfaceSCIESCOPUS

IEEE Journal of Solid-State Circuits, vol. 51, no. 8, page. 1890 - 1901, 2016-08

Conference
A Wide Range Delay Locked Loop for DDR4

반도체학술대회, 2017-02-13

Article
Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY InterfaceSCIESCOPUS

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 14, no. 4, page. 463 - 470, 2014-08

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