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Showing results 4 to 17 of 17

Conference

Improving Program Efficiency of 3D NAND Cell Structure Based on Artificial Neural Network

2021년도 대한전자공학회 하계종합학술대회, 2021-07-01

Conference

Neural Network Based 14-nm Node Fully-Depleted FET Design for AC Applications of SoC and 3DIC

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

Conference

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications

4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020, 2020-03-17

Article

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC ApplicationsSCIESCOPUS

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, vol. 8, page. 1272 - 1280, 2020-09

Article

Observation of mobility and velocity behaviors in ultra-scaled L-G=15 nm silicon nanowire field-effect transistors with different channel diametersSCIESCOPUS

SOLID-STATE ELECTRONICS, vol. 164, 2020-02

Conference

Optimal Energetic Trap Distribution of Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using Machine Learning Methodology

2021 International Conference on Solid State Devices and Materials, 2021-09-08

Article

Polysilicon near-infrared photodetector with performance comparable to crystalline silicon devicesSCIESCOPUS

OPTICS EXPRESS, vol. 25, no. 26, page. 32910 - 32918, 2017-12

Conference

Power, Performance and Area Analysis of Source/Drain Patterning n/p FinFETs based 6T-SRAM cell for 3-nm technology node

제 27회 반도체학술대회, 2020-02-14

Article

Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETsSCIESCOPUS

IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 67, no. 1, page. 258 - 262, 2020-01

Article

Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm NodeSCIESCOPUS

IEEE ACCESS, vol. 7, page. 172290 - 172295, 2019-12

Conference

SRAM Performance Variations Induced by Source/Drain Mole Fraction Change of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

Conference

The Origin of Incremental Step Pulse Programming (ISPP) Slope Degradation in NAND Flash Memory

제 27회 반도체학술대회, 2020-02-13

Article

Threshold Voltage Variations Induced by Si1-xGex and Si1-xCx of Sub 5-nm Node Silicon Nanosheet Field-Effect TransistorsSCIE

JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, vol. 20, no. 8, page. 4684 - 4689, 2020-08

Conference

TSV-to-Transistor Noise Coupling Characterizations for Sub 5-nm Node Fin- and Nanosheet FETs in 3D-IC

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

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Browsing by AuthorYOON, JUN SIK

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