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Browsing by  AuthorJINSU, JEONG

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Showing results 2 to 9 of 9
Conference
Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications

4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020, 2020-03-17

Article
Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC ApplicationsSCIESCOPUS

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, vol. 8, page. 1272 - 1280, 2020-09

Article
Observation of mobility and velocity behaviors in ultra-scaled L-G=15 nm silicon nanowire field-effect transistors with different channel diametersSCIESCOPUS

SOLID-STATE ELECTRONICS, vol. 164, 2020-02

Conference
Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs

The 7th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2023), 2023-03-09

Conference
Power, Performance and Area Analysis of Source/Drain Patterning n/p FinFETs based 6T-SRAM cell for 3-nm technology node

제 27회 반도체학술대회, 2020-02-14

Article
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm NodeSCIESCOPUS

IEEE ACCESS, vol. 7, page. 172290 - 172295, 2019-12

Article
Threshold Voltage Variations Induced by Si1-xGex and Si1-xCx of Sub 5-nm Node Silicon Nanosheet Field-Effect TransistorsSCIE

JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, vol. 20, no. 8, page. 4684 - 4689, 2020-08

Conference
TSV-to-Transistor Noise Coupling Characterizations for Sub 5-nm Node Fin- and Nanosheet FETs in 3D-IC

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

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