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YOO, SUNGJOO (유승주)

Dept of Electrical Engineering(전자전기공학과)

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Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||Dynamic voltage and frequency scaling (DVFS):4||runtime distribution:4||LEVEL:3||energy optimization:3||motion estimation:3||PERFORMANCE:3||POWER MANAGEMENT:2||INTERPOLATION:2||phasechange RAM (PRAM):2||onchip communication:2||Frame rate upconversion:2||QUALITY:2||SYSTEMS:2||VIDEO:2||optimistic simulation:2||multiprocessor systemonchip:2||synchronization overhead:2||write endurance:2||networkonchip:2||differential writes:2||Data encoding:2||motioncompensated interpolation:2||simulation:1||SUPPLY VOLTAGE:1||DYNAMIC THERMAL MANAGEMENT:1||power gating (PG):1||operating systems:1||DESIGN:1||Solidstate disk:1||COMPUTERS:1||performance:1||chipmultiprocessor:1||VOLTAGE:1||memory stall:1||design automation:1||PERFORMANCE ESTIMATION:1||scalable distributed simulation:1||OS generation:1||multiprocessor architecture:1||targeting:1||memory blocking:1||idletime:1||COSIMULATION:1||geographically distributed cosimulation:1||PREDICTION:1||hard real time:1||fix modify restart scenario:1||multiprocessor SystemsonChip:1||systemonachip (SoC):1||Performance:1||DRAM:1||shared memory system:1||MICROARCHITECTURE:1||RUNTIME DISTRIBUTION:1||ENERGY:1||scheduler implementation:1||onchip communication delay model:1||hierarchical simulation environment:1||multiprocessor:1||Embedded systems:1||onchip networks:1||scene change detection:1||TRANSLATION LAYER:1||dynamic voltage and frequency scaling (DVFS):1||HARDWARE/SOFTWARE CODESIGN:1||PICONET:1||hybrid cosimulation:1||saving states/traces:1||COSIMULATION:1||embedded systems:1||state saving:1||cosimulation:1||rollback:1||power management:1||thermal management:1||transactionlevel model:1||Computer architecture:1||scheduling:1||hardware resource constraints:1||parallelism:1||Motion compensated interpolation:1||NAND flash memory:1||MEMORY:1||timed cosimulation:1||Active memory operation:1||MULTIPROCESSORS:1||THERMAL MANAGEMENT:1||3D integration:1||phase:1||OS model:1||synthesis:1||correlation:1||hardware/software:1||energy minimization:1||cycleapproximate simulation:1||dynamic software synchronization:1||grouped message:1||hardware:1||shot change detection:1||memory access scheduling:1||Design:1||

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