Open Access System for Information Sharing
All
Title
Author
Subject
Login
Library
Help
검색
HOME
Communities & Collections
Researchers
Title
Browse by Researchers
PARK, HONG JUNE (박홍준)
Dept of Electrical Engineering(전자전기공학과)
Field(s)
E-Mail
Homepage
Loading...
Export
Journal Papers
(International)
Journal Papers
(Domestic)
Conference Papers
(International)
Conference Papers
(Domestic)
Journal Papers(International)
Journal Papers(Domestic)
Conference Papers(International)
Conference Papers(Domestic)
20 items
100 items
200 items
Show more items...
Keyword
CMOS:13||DESIGN:11||Crosstalk:8||TRANSCEIVER:6||transceiver:6||timetodigital converter:6||TODIGITAL CONVERTER:6||time amplifier:6||PLL:5||microstrip line:5||singleended signaling:5||crosstalkinduced jitter:4||current mode:4||Alldigital PLL:4||CONVERTER:4||TIME:4||sensor interface:4||parallel links:4||crosstalkinduced jitter (CIJ):4||successive approximation register (SAR):4||wireline:4||fractionalN PLL:4||farend crosstalk:4||frequency synthesizer:4||microstrip:4||FRONTEND:4||termination:4||silicon interposer:4||transmission line:4||Analogtodigital converter (ADC):4||phase noise:4||COMPENSATION:4||CANCELLATION:3||intersymbol interference (ISI):3||RECOVERY:3||printed circuit board:3||I/O:3||low voltage:3||signal integrity:3||Adaptive equalization:3||DRAM interface:3||TRANSMITTER:3||LOCKED LOOP:3||REDUCE:2||ADAPTIVE EQUALIZATION:2||LINKS:2||gate leakage:2||Analogtodigital converter:2||differential:2||buffer circuits:2||timing jitter:2||Dynamic element matching:2||ultrasound:2||analog frontend:2||Gmbased amplifier:2||quantization noise:2||Clock and data recoveries (CDRs):2||DLL:2||thinfilmtransistor LCD:2||digital phaselocked loop (DPLL):2||fractionalN phaselocked loop (PLL):2||transmitter:2||LVDS:2||CMOS LATCHUP:2||Transmitter:2||transimpedance amplifier (TIA):2||Interconnect model:2||SIMULATION:2||CIRCUITS:2||operational transconductance amplifier (OTA):2||semidigital amplifier:2||ClockAlignedtoData Intrapanel (CADI):2||deskew:2||CROSSTALKINDUCED JITTER:2||FAREND CROSSTALK:2||DRAM chips:2||comparator:2||inverterbased:2||singleended I/O:2||throughsilicon via (TSV):2||duobinary:2||high resolution Time to Digital Converter (TDC):2||wide input range:2||Capacitor mismatch compensation:2||nonbinaryweighted capacitor array:2||INTERCONNECTS:2||FREQUENCYSYNTHESIZER:2||Adaptive crosstalk cancellation:2||CDRs:2||lowpower links:2||memory interface:2||ADPLL:2||SUCCESSIVE APPROXIMATION ADC:2||intrapanel interface:2||pointtopoint:2||VSYNC:2||noise cancellation:2||three state:2||CMOS integrated circuits:2||preemphasis:2||timedomain reflectometry (TDR):2||successive approximation ADC:2||digital:2||MICROSTRIP LINES:2||lowswing I/O:2||onchip I/O:2||onchip interconnect:2||open loop:2||Channel model:2||RCdominant wires:2||phase interpolator:2||FIR filtering:2||splitcapacitor digitaltoanalog converter (DAC):2||SENSOR:2||subexponent TDC:2||clock timing control:2||slew rate control:2||Variable gain amplifier:2||signaling modes:2||CHARGEPUMP:2||digitaldomain calibration:2||Deltasigma timetodigital converter (TDC):2||Charge pump:2||power distribution lines:2||SAR ADC:2||onchip link:2||PERFORMANCE:2||high resolution:2||50 MS/S:2||Deltasigma modulation:2||SYNTHESIZER:2||SERPENTINE GUARD TRACE:2||VOLTAGE:2||CROSSTALK:2||FREQUENCYSYNTHESIS:2||output driver:2||CMOS memory integrated circuits:2||serpentine guard trace:2||lowenergy I/O:2||NM CMOS:2||WIRES:2||ultralow power:2||digitally controlled:2||medical imaging:2||wireline transceiver design:2||phaselocked loop (PLL):2||LINES:2||Deltasigma modulator:2||digital PLL:2||CHIP:2||PIN SKEW COMPENSATION:2||LINK:2||peak detector:2||current comparator:2||diode rectifier:2||levelshifter:2||simultaneous switching noise:2||pseudoresistor:2||lowvoltage OTA:2||DRAM:2||FORMULAS:2||bidirectional:2||CMOS transceivers:2||Analog to digital conversion:2||lowpower input/output (I/O):2||TRANSMISSIONLINES:2||pipelined ADC:2||OPAMP:2||OPAMP:2||noiseshaping:2||Crosstalkinduced jitter:2||JITTER:2||Electrocardiogram amplifier:2||modeling:2||integrated circuit reliability:2||dual inline memory module (DIMM) connector:2||Emulation:2||Memory interface:2||Gain control:2||analogtodigital converter (ADC):2||currentmode:1||MUX embedded D flipflop:1||DIGITAL DLL:1||DIVIDER:1||clock synchronization:1||phase detector:1||seamless phase change:1||stubless channel:1||DECISIONFEEDBACK EQUALIZER:1||tristate inverter:1||Ionsensitive fets:1||First order systems:1||Pipelines:1||Staticpower dissipation:1||gigabit DRAMs:1||PRESCALER:1||empirical:1||multidrop bus:1||BACKPLANE:1||CLOCK GENERATOR:1||preemphasis equalizer:1||RX input sensitivity:1||phaselocked loop:1||Current steering DAC:1||lookahead decision feedback equalization (DFE):1||reference circuits:1||stability:1||fixeddelay rising edge:1||PULSEWIDTH CONTROL LOOP:1||adaptive bandwidth:1||LINE:1||SERIAL LINK:1||interpolation:1||continuous time linear equalizer (CTLE):1||referenceless CDR:1||Successive approximation register:1||Current steering digitaltoanalog converters:1||Selfbiasing circuits:1||DUOBINARY:1||digital PWCL:1||equalizer:1||LOWPOWER:1||USB 2.0 highspeed PHY:1||preamplifier:1||clock and data recovery (CDR):1||frequency acquisition:1||standard cell:1||Frequency converters:1||DEVICE CHARACTERISTICS:1||Timing circuits:1||Frequency compensation:1||Bias voltage:1||65 NM CMOS:1||complementary commonmode:1||dualloop DLL:1||DELAYLOCKED LOOP:1||INTERFACE:1||wide range:1||PHASELOCKEDLOOP:1||Verilog:1||Currentintegrating:1||differential transceiver:1||lowpower:1||Comparator circuits:1||Low power sensor:1||CHANNEL:1||Continuous time systems:1||Digital converters:1||Wide dynamic range:1||IIR:1||LOWVOLTAGE:1||charge pump:1||counting circuits:1||highspeed electronics:1||crosstalk:1||interconnect:1||INDUCTANCE:1||analog voltagecontrolled delay line (VCDL):1||plesiochronous:1||Alldigital phaselocked loop (ADPLL):1||digitally controlled oscillator (DCO):1||INDUCED JITTER:1||Approximation theory:1||Comparators (optical):1||Signal to noise ratio:1||Surveying:1||Analog to digital converters:1||Static power consumption:1||Switched capacitor circuits:1||boosted voltage generator:1||three data over four conductors:1||digital circuits:1||mutual capacitance:1||mutual inductance:1||pulsewidth control loop (PWCL):1||infinite phase shift:1||DDR3 SDRAM:1||mixedmode simulation:1||lowswing:1||TIA:1||rotational frequency detector (RFD):1||Alldigital:1||fractionalN:1||synthesis:1||Nyquist rate:1||RRAM:1||MEMORIES:1||Low power electronics:1||Digital to analog conversion:1||Pipeline analogtodigital converters:1||PJ/BIT:1||differential signaling:1||preemphasis:1||frequency division:1||delaylocked loop (DLL):1||jitter:1||OPERATION:1||integration:1||Decisionfeedback equalization (DFE):1||SCHEME:1||BUS:1||asynchronous sampling:1||timetodigital converter (TDC):1||Capacitance:1||Quantization errors:1||Figure of merits:1||Transimpedance stages:1||DFE:1||
Publication & Time Cited Count
(For the Last 5 years)
Browse
Communities & Collections
Researcher
Title
Login
Library
Help