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PARK, HONG JUNE(박홍준)

Department: Dept of Electrical Enginrg(전자전기공학과)

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DESIGN:6||CMOS:6||Crosstalk:4||singleended signaling:3||transmission line:3||microstrip line:3||TODIGITAL CONVERTER:3||timetodigital converter:3||PLL:3||transceiver:3||TRANSCEIVER:3||time amplifier:3||parallel links:2||silicon interposer:2||successive approximation register (SAR):2||frequency synthesizer:2||microstrip:2||DRAM interface:2||farend crosstalk:2||wireline:2||fractionalN PLL:2||CMOS integrated circuits:2||FRONTEND:2||low voltage:2||TRANSMITTER:2||current mode:2||phase noise:2||Analogtodigital converter (ADC):2||termination:2||sensor interface:2||crosstalkinduced jitter (CIJ):2||printed circuit board:2||LOCKED LOOP:2||CONVERTER:2||TIME:2||FORMULAS:2||DRAM:2||intersymbol interference (ISI):2||Alldigital PLL:2||COMPENSATION:2||crosstalkinduced jitter:2||signal integrity:2||DIGITAL DLL:1||DIVIDER:1||currentmode:1||MUX embedded D flipflop:1||clock synchronization:1||phase detector:1||seamless phase change:1||Charge pump:1||stubless channel:1||DECISIONFEEDBACK EQUALIZER:1||tristate inverter:1||power distribution lines:1||SAR ADC:1||CANCELLATION:1||CHARGEPUMP:1||digitaldomain calibration:1||signaling modes:1||Deltasigma timetodigital converter (TDC):1||slew rate control:1||Variable gain amplifier:1||gigabit DRAMs:1||PRESCALER:1||empirical:1||FREQUENCYSYNTHESIS:1||SERPENTINE GUARD TRACE:1||multidrop bus:1||BACKPLANE:1||CLOCK GENERATOR:1||output driver:1||serpentine guard trace:1||CROSSTALK:1||VOLTAGE:1||CMOS memory integrated circuits:1||RECOVERY:1||SYNTHESIZER:1||Deltasigma modulation:1||50 MS/S:1||PERFORMANCE:1||high resolution:1||onchip link:1||reference circuits:1||fixeddelay rising edge:1||stability:1||PULSEWIDTH CONTROL LOOP:1||lookahead decision feedback equalization (DFE):1||adaptive bandwidth:1||LINE:1||current comparator:1||diode rectifier:1||peak detector:1||pseudoresistor:1||lowvoltage OTA:1||SERIAL LINK:1||interpolation:1||levelshifter:1||simultaneous switching noise:1||bidirectional:1||CMOS transceivers:1||PIN SKEW COMPENSATION:1||LINK:1||Deltasigma modulator:1||digital PLL:1||phaselocked loop (PLL):1||CHIP:1||wireline transceiver design:1||LINES:1||lowenergy I/O:1||NM CMOS:1||WIRES:1||ultralow power:1||digitally controlled:1||medical imaging:1||digital PWCL:1||Electrocardiogram amplifier:1||equalizer:1||LOWPOWER:1||dual inline memory module (DIMM) connector:1||Crosstalkinduced jitter:1||JITTER:1||integrated circuit reliability:1||modeling:1||noiseshaping:1||pipelined ADC:1||OPAMP:1||OPAMP:1||USB 2.0 highspeed PHY:1||lowpower input/output (I/O):1||TRANSMISSIONLINES:1||I/O:1||complementary commonmode:1||dualloop DLL:1||DELAYLOCKED LOOP:1||INTERFACE:1||wide range:1||PHASELOCKEDLOOP:1||LVDS:1||CMOS LATCHUP:1||Adaptive equalization:1||DLL:1||thinfilmtransistor LCD:1||transmitter:1||quantization noise:1||Clock and data recoveries (CDRs):1||Gmbased amplifier:1||digital phaselocked loop (DPLL):1||fractionalN phaselocked loop (PLL):1||Transmitter:1||Verilog:1||Emulation:1||Gain control:1||analogtodigital converter (ADC):1||ultrasound:1||analog frontend:1||Memory interface:1||charge pump:1||counting circuits:1||highspeed electronics:1||crosstalk:1||interconnect:1||INDUCTANCE:1||analog voltagecontrolled delay line (VCDL):1||plesiochronous:1||CROSSTALKINDUCED JITTER:1||FAREND CROSSTALK:1||Alldigital phaselocked loop (ADPLL):1||digitally controlled oscillator (DCO):1||DRAM chips:1||INDUCED JITTER:1||ClockAlignedtoData Intrapanel (CADI):1||deskew:1||comparator:1||operational transconductance amplifier (OTA):1||semidigital amplifier:1||inverterbased:1||transimpedance amplifier (TIA):1||Interconnect model:1||SIMULATION:1||CIRCUITS:1||boosted voltage generator:1||digital circuits:1||mutual capacitance:1||mutual inductance:1||pulsewidth control loop (PWCL):1||three data over four conductors:1||infinite phase shift:1||three state:1||DDR3 SDRAM:1||MICROSTRIP LINES:1||preemphasis:1||timedomain reflectometry (TDR):1||intrapanel interface:1||pointtopoint:1||VSYNC:1||successive approximation ADC:1||ADPLL:1||FREQUENCYSYNTHESIZER:1||lowpower links:1||memory interface:1||SUCCESSIVE APPROXIMATION ADC:1||INTERCONNECTS:1||Adaptive crosstalk cancellation:1||CDRs:1||noise cancellation:1||digital:1||mixedmode simulation:1||singleended I/O:1||throughsilicon via (TSV):1||duobinary:1||high resolution Time to Digital Converter (TDC):1||wide input range:1||Capacitor mismatch compensation:1||nonbinaryweighted capacitor array:1||frequency division:1||differential signaling:1||preemphasis:1||delaylocked loop (DLL):1||jitter:1||OPERATION:1||gate leakage:1||clock timing control:1||REDUCE:1||Decisionfeedback equalization (DFE):1||integration:1||SCHEME:1||BUS:1||timing jitter:1||buffer circuits:1||ADAPTIVE EQUALIZATION:1||LINKS:1||Analogtodigital converter:1||FIR filtering:1||phase interpolator:1||splitcapacitor digitaltoanalog converter (DAC):1||SENSOR:1||Channel model:1||RCdominant wires:1||subexponent TDC:1||differential:1||lowswing I/O:1||onchip I/O:1||onchip interconnect:1||open loop:1||

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