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네트워크 채널 다결정실리콘 박막 트랜지스터의 제작 및 특성 분석

Title
네트워크 채널 다결정실리콘 박막 트랜지스터의 제작 및 특성 분석
Authors
이준영
Date Issued
2018
Publisher
포항공과대학교
Abstract
The demands for high electrical characteristics of thin-film transistors (TFTs) have been increased in display and memory industries. There are various TFT applications including liquid-crystal display (LCD), organic light emitting diode (OLED), non-volatile memory. Polysilicon has a much higher mobility than amorphous silicon and oxide, which is advantageous for manufacturing high-performance TFTs. Poly-Si TFTs use a poly-Si channels crystallized from a-Si by various methods such as solid-phase crystallization (SPC) and excimer-laser annealing (ELA). Poly-Si TFTs are attracting attention in the LCD requiring high resolution or OLED panel which requires precise current control using TFT. Thus, scale down of poly-Si TFTs has been continuously progressed to obtain the high resolution devices. However, scaling down has difficulty in progressing due to several constraints such as lithography technology, high-cost process. In this study, a study on fabrication and characterization of network-channel poly-Si TFTs were investigated to obtain high-performance devices. By forming the network-channel with regular hexagonal patterns using e-beam lithography, we expected that grain boundaries in the channel could be removed and electrical properties improve compared to conventional TFTs. First, we fabricated n-type network-channel poly-Si TFTs by using SPC poly-Si channel on silicon substrate. Electrical characteristics and positive bias-temperature instability (PBTI) of network-channel TFTs were studied depending on three different hole sizes (SH = 0.2, 0.5, and 0.8 μm) and compared to conventional TFTs. As SH increased, subthreshold swing (SS) and on-current (ION) were improved greatly due to the reduced grain boundary trap density (NGB) and the enhanced gate-to-channel controllability by tri-gate effect. The extracted NGB for SH = 0.8 μm was ~30% lower than that of conventional TFTs. In addition, threshold voltage shift (ΔVTH) and NGB change (ΔNGB) were investigated by applying stress voltage 15 V during 3000 s at T = 25 and 100 °C respectively. The network-channel TFTs with larger SH showed higher reliability characteristics with lower ΔVTH and ΔNGB under PBTI stress. Second, the impacts of geometrical parameters on the electrical performances of network-channel low-temperature polysilicon (LTPS) TFTs were studied. In order to investigate the effects of parameters such as hole-to-hole distance, hole-branch top width, effective channel width, and area filling factor (AF), the grain boundary trap density and interface trap density were also extracted. It was observed that the electrical characteristics were considerably dependent on AF due to reduction of trap densities. However, excessive hole formation in the network-channel gave rise to the increase of the channel resistance and degradation of the drain current. We proposed a design guideline to found high performance of network-channel poly-Si TFTs with various network-channel dimensions. Therefore, it can be concluded that denser hole patterns are preferred for obtaining high performances of network-channel LTPS TFTs. These results demonstrate that the high-performance network-channel TFTs can become high potential devices of being applied to next-generation displays.
URI
http://postech.dcollection.net/common/orgView/200000108836
http://oasis.postech.ac.kr/handle/2014.oak/93372
Article Type
Thesis
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