10 to 250MHz of Lock Range 0.4um Triple Well CMOS PLL
- 10 to 250MHz of Lock Range 0.4um Triple Well CMOS PLL
- POSTECH Authors
- Date Issued
- 제4회 한국반도체 학술대회
- Article Type
- 제 4회 반도체 학술대회, 1997-02-01
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