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Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis

Title
Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis
Authors
김영환Kai Chen
POSTECH Authors
김영환
Date Issued
28-Apr-2015
Publisher
IEEE Circuits and Systems Society
URI
http://oasis.postech.ac.kr/handle/2014.oak/71470
Article Type
Conference
Citation
VLSI Design, Automation and Test (VLSI-DAT 2015), 2015-04-28
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Dept of Electrical Enginrg
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