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dc.contributor.author김영환ko
dc.contributor.authorKai Chenko
dc.date.accessioned2018-06-19T03:49:52Z-
dc.date.available2018-06-19T03:49:52Z-
dc.date.created2016-02-29-
dc.date.issued2015-07-01-
dc.identifier.citation11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), pp.121 - 124-
dc.identifier.urihttp://oasis.postech.ac.kr/handle/2014.oak/71428-
dc.publisherIEEE Circuits and Systems Society-
dc.titleBalanced Current Source Model of the Three-input Combinational Logic Gate for Timing Analysis-
dc.typeConference-
dc.type.rimsCONF-
dc.contributor.localauthor김영환-
dc.contributor.nonIdAuthorKai Chen-
dc.citation.endPage124-
dc.citation.startPage121-
dc.citation.title11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015)-
dc.description.journalClass1-
dc.identifier.conferencecountryUK-

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