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Balanced Current Source Model of the Three-input Combinational Logic Gate for Timing Analysis

Title
Balanced Current Source Model of the Three-input Combinational Logic Gate for Timing Analysis
Authors
김영환Kai Chen
POSTECH Authors
김영환
Date Issued
1-Jul-2015
Publisher
IEEE Circuits and Systems Society
URI
http://oasis.postech.ac.kr/handle/2014.oak/71428
Article Type
Conference
Citation
11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), page. 121 - 124, 2015-07-01
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 KIM, YOUNG HWAN
Dept of Electrical Enginrg
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