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Verilog Synthesis of USB 2.0 Full-speed Device PHY IP

Title
Verilog Synthesis of USB 2.0 Full-speed Device PHY IP
Authors
김병섭신기범성기환여동희심재윤박홍준
POSTECH Authors
김병섭심재윤박홍준
Date Issued
19-Nov-2013
Publisher
IEEE
URI
http://oasis.postech.ac.kr/handle/2014.oak/68990
Article Type
Conference
Citation
International SoC Design Conference, 2013-11-19
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