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dc.contributor.author성기환ko
dc.contributor.author임지훈ko
dc.contributor.author김병섭ko
dc.contributor.author심재윤ko
dc.contributor.author박홍준ko
dc.date.accessioned2018-06-19T00:06:45Z-
dc.date.available2018-06-19T00:06:45Z-
dc.date.created2015-02-20-
dc.date.issued2014-05-17-
dc.identifier.citation2014 SoC 학술대회-
dc.identifier.urihttp://oasis.postech.ac.kr/handle/2014.oak/68472-
dc.publisher대한전자공학회 SoC설계연구회-
dc.titleUSB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling-
dc.typeConference-
dc.type.rimsCONF-
dc.contributor.localauthor김병섭-
dc.contributor.localauthor심재윤-
dc.contributor.localauthor박홍준-
dc.citation.title2014 SoC 학술대회-
dc.description.journalClass2-
dc.identifier.conferencecountryKO-

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