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USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling

Title
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling
Authors
심재윤성기환김병섭임지훈박홍준
POSTECH Authors
심재윤김병섭박홍준
Date Issued
17-May-2014
Publisher
대한전자공학회
URI
http://oasis.postech.ac.kr/handle/2014.oak/67934
Article Type
Conference
Citation
대한전자공학회 SoC 학술대회, 2014-05-17
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