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Verilog Synthesis of USB 2.0 Full-speed Device PHY IP

Title
Verilog Synthesis of USB 2.0 Full-speed Device PHY IP
Authors
박홍준신기범성기환여동희김병섭심재윤
POSTECH Authors
박홍준
Date Issued
18-Nov-2013
Publisher
IEIE & IEEE, Int. SoC Design Conference(ISOCC)
URI
http://oasis.postech.ac.kr/handle/2014.oak/65267
Article Type
Conference
Citation
IEIE & IEEE, Int. SoC Design Conference(ISOCC), 2013-11-18
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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