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Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits

Title
Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits
Authors
심재윤여동희성기환전성환김종훈박홍준
POSTECH Authors
심재윤박홍준
Date Issued
22-Jun-2011
Publisher
International Technical Conference on Circuits/Systems, Computers and Communications
URI
http://oasis.postech.ac.kr/handle/2014.oak/60504
Article Type
Conference
Citation
International Technical Conference on Circuits/Systems, Computers and Communications, 2011-06-22
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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