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실리콘 나노와이어 FET 제작 및 그 전기적 특성

Title
실리콘 나노와이어 FET 제작 및 그 전기적 특성
Authors
박찬훈
Date Issued
2010
Publisher
포항공과대학교
Abstract
In this paper, inductively coupled plasma (ICP) etching step optimization process, fabrication and characterization of 3-dimensional silicon nanowire FET (Si-NWFET) with sub-30nm omega-shaped gate are studied. Profile evolution and high selectivity during poly-silicon gate over silicon dioxide (SiO2) etching has been investigated with low-pressure high-density HBr/O2 plasma chemistries. The gate stack with HfO2 dry etching step, etching profile shows nearly vertical slope when applying optimized etching recipe. This recipe consisted of HBr/Cl2/O2 poly-silicon etching step, residue gas purging step and Cl2 metal gate etching step. The sub-30nm n-type Si-NWFET with 4nm gate oxide shows an on-state current of 1.25×10-1 mA/μm at Vg=Vd=1.2V and the off-state current of 1×10-6 mA/μm, which is normalized by the active channel width. Extremely low drain induced barrier lowering (DIBL) is 2.22mV/V and subthreshold slope (SS) 91.4mV/dec indicates the excellent gate controllability of nanowire FET. The Si-NWFET reliability on the condition of constant voltage stress (CVS, at Vg=4.2V) and hot carrier induced stress (HCI, at Vg=4.2V, Vd=4.5V) is studied. No degradation occurred under these stresses which show that Si-NWFET has excellent reliability characteristic. The 1/f noise measurement is performed to extract volume trap density in the gate oxide. The average value of volume trap density is about 5.14×1017cm-3eV-1, which is similar value to Samsung twin silicon nanowire FET (TSNWFET) device with different geometry. This result verifies uniformity of our process. The series resistance (Rsd) is a crucial parameter in highly scaled field effect transistors, especially due to the contact configuration between the source/drain and the channel region. The extracted Rsd in Si-NWFET using the Y-function technique, in concurrence with the measured electrical data. The Rsd values are shown to almost flat under the influence of the applied gate voltage. The simulated Id-Vg is also well fitted to the measured electrical values and confirms the validity of Rsd extraction method.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000547030
http://oasis.postech.ac.kr/handle/2014.oak/594
Article Type
Thesis
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