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Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits

Title
Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits
Authors
박홍준여동희성기환전성환김종훈심재윤
POSTECH Authors
박홍준심재윤
Date Issued
22-Jun-2011
Publisher
대한전자공학회
URI
http://oasis.postech.ac.kr/handle/2014.oak/58886
Article Type
Conference
Citation
ITC-CSCC, 2011-06-22
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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