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Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design

Title
Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design
Authors
김영환김재훈
POSTECH Authors
김영환
Date Issued
4-Aug-2010
Publisher
Asqed
URI
http://oasis.postech.ac.kr/handle/2014.oak/57303
Article Type
Conference
Citation
Asia Symposium on Quality Electronic Design(Asqed) 2010, page. 314 - 317, 2010-08-04
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 KIM, YOUNG HWAN
Dept of Electrical Enginrg
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