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Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Title
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
Authors
김장우
POSTECH Authors
김장우
Date Issued
4-Dec-2007
Publisher
IEEE Computer Society
URI
http://oasis.postech.ac.kr/handle/2014.oak/56881
Article Type
Conference
Citation
IEEE/ACM International Symposium on Microarchitecture, page. 197 - 209, 2007-12-04
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김장우KIM, JANGWOO
Dept of Computer Science & Enginrg
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