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다중 전원 전압 시스템을 위한 레벨 변환기의 설계

다중 전원 전압 시스템을 위한 레벨 변환기의 설계
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As the use of the mobile electronic devices increases very rapidly, low-power becomes one of the most important design issues of today’s CMOS VLSI circuits. Lowering the supply voltage (VDD) is a simple and very efficient way to reduce the power consumption, because it reduces dynamic power in quadratic and leakage power exponentially. However, lowering the VDD of the whole system degrades the operating speed of the system. To reduce the power consumption without the speed degradation, the multi-supply voltage (multi-VDD) approach that uses more than one power-supply voltage in the same system was proposed. In the multi-VDD system, we apply low-VDD (VDDL) to the logic gates on the non-critical paths, while we apply high-VDD (VDDH) to the logic gates on the critical paths. Although multi-VDD can be applied at the gate level, the voltage island approach, applying the multi-VDD system at the large macro level, is more widely used nowadays. The multi-VDD system has a problem that is the large static current flow through a weakly turned-on PMOS transistor when a VDDH block is driven by the logic ‘1’ (VDDL, high) signal of a VDDL block. To prevent this static current flow, the level converter (LC) which converts a VDDL signal to a VDDH signal is necessary. However, the use of the LCs increases the overheads of power consumption, delay, and area. Therefore, one of the main challenges in multi-VDD system is to reduce the overheads caused by using the LCs. The LC is classified into asynchronous and synchronous LCs. The asynchronous LC is a combinational circuit which accepts the VDDL input signal, and then provides the VDDH output signal. The synchronous LC is a special flip-flop (FF) in which the level conversion is embedded. It takes the VDDL input and the VDDL clock signals, and provides the VDDH output signal. Typically, the synchronous LC is called the level converting FF (LCFF). In the multi-VDD system, the LCFF can be used instead of the LC and VDDL FF. If we use LCFF instead of the LC and FF, the overheads of using the LC can be reduced. In this paper, LC represents an asynchronous LC and LCFF represents a synchronous LC. In this paper, we propose three low-power and high-performance level converting elements, which are two LCs and one LCFF: Single supply junction-based level converter (SJLC), Single-supply PMOS pass-transistor level converter (SPLC), and Explicit pulse-triggered dual-pass-transistor flip-flop (EPDFF). As they provide the advantages of lower power and higher speed compared to existing level converting elements, they can reduce the overheads induced by LCs or LCFFs. Specifically, since the proposed LCs use only one power-supply voltage, they provide the advantage of reducing the complexity in physical design, compared to the typical LCs that use two power-supply voltages. The proposed EPDFF consists of a newly-invented simple explicit pulse generator and a latch of dual pass-transistors. As an explicit pulse-triggered type, the proposed LCFF can share a pulse generator with other EPDFFs to reduce power consumption and area. In experiments, SJLC showed 43.8% lower power-delay product and 53.5% smaller transistor area than the benchmark circuit. In case of SPLC, it showed 19% lower power-delay product and 43.3% smaller transistor area than the benchmark circuit. In addition, EPDFF showed 43~71% lower power-delay product and 26~61% smaller transistor area than the seven benchmark LCFFs.
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