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Interleaving Partial Bus Invert Coding for Low Power Reconfiguration of FPGAs

Title
Interleaving Partial Bus Invert Coding for Low Power Reconfiguration of FPGAs
Authors
유승주
POSTECH Authors
유승주
Date Issued
10-Oct-1999
Publisher
ICVC
URI
http://oasis.postech.ac.kr/handle/2014.oak/53272
Article Type
Conference
Citation
International Conference on VLSI and CAD (ICVC), 1999-10-10
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 YOO, SUNGJOO
Dept of Electrical Enginrg
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