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광대역 신호처리를 위한 디지털 RF 수신기에 관한 연구

Title
광대역 신호처리를 위한 디지털 RF 수신기에 관한 연구
Authors
박창준
Date Issued
2010
Publisher
포항공과대학교
Abstract
As the multi-functional communication systems are developed, mobile terminals should be operated at multi-band multi-mode to handle the various systems. The software defined radio (SDR) system is introduced as an ultimate goal of multi-mode multi-band receiver systems. However, the technical limits in SDR system prevent the existence. A digital RF sampling receiver is suggested as a middle stage technique for the SDR. To satisfy the global communication market demands, highly integrated digital RF systems are being developed very rapidly. In this thesis, the simple architecture and concept of the digital RF receiver are introduced with comparison of the existing receiver systems. An approach to map the Bluetooth (BT) and mobile-WiMAX (WiBro) standards specifications into the architecture and specifications for the building blocks of a digital RF receiver are proposed. The design procedure focuses on optimization of the performance in each standard while attaining an efficient shared RF front-end solutions. Especially, analysis for two key building blocks for the digital RF receiver system is presented and applied in the designed building blocks. The proposed receiver design is verified through each circuit and a fully integrated implementation using IBM 130-nm and Samsung 65-nm CMOS technology. Firstly, architecture of the digital RF receiver systems are introduced and compared with other receiver systems. It is shown that the digital RF receiver architecture is suitable for the next generation system because of its reliability and digital tunability. Among various applications, we choose BT for narrowband characteristics and WiBro for its popularity and inherent wideband characteristics. Therefore architecture and system considerations of digital RF receiver are introduced. This thesis presents circuit designs, including RF front-end and baseband circuits, for BT and WiBro applications. The wideband low noise amplifier (LNA) is designed to cover poor linearity and noise figure and achieves 4 dBm IIP3 and under 3.8 dB noise figure in 0.7-3.5 GHz. The blocker filtering LNA is designed to remove the SAW filter in BT standard and achieves 1.46 dBm IIP3, 1.85 dB noise figure, -8.2 dBm P1dB and -13 dBc attenuation level at sideband. The charge-domain passive mixer (CDPM) with a trans-conductance amplifier (TA) block is designed to mitigate the critical flicker noise problem that is frequently encountered the direct conversion receivers and achieves a low flicker noise with corner frequency of under 100 kHz, 8.1 dB noise figure, 10.6 dB conversion gain, 2.5 dBm IIP3, and -5.7 dBm P1dB with 2.4 GHz LO driving at 5 dBm. In the baseband region, DC offset is resolved via feedback loop with resistors and capacitors at variable gain amplifier block and the filtering requirements for both applications are achieved by the proposed discrete-time (DT) filters with non-decimation filters and an anti-aliasing filter. This thesis also presents analysis of the performance of a charge-domain passive mixer with a capacitive load. We analyze performance of the mixer in terms of conversion gain and the 1 dB compression point and show the accuracy of our analysis by comparing with simulated results for a 130-nm technology based mixer design. The load capacitance influences the conversion gain of the mixer, and the bias voltage affects it linearly. The results provide a theoretical basis for CDPM in the digital RF receiver. Finally, a new FIR filter has been developed to realize a DT filter for wideband signal processing, and compared the conventional FIR filter and proposed FIR filter for filtering characteristic with numerical expressions. The filter maintains the moving average effect, but the decimation function is removed to realize a cascadable filter. The design is fabricated with a 65-nm CMOS process. By cascading the proposed FIR filter with a conventional FIR filter, about -60 dB attenuation across 50 MHz signal bandwidth is possible at the sampling rate of 600 Ms/s, and the noise generated by adding the proposed FIR filter is negligible. By the cascade more stages, the bandwidth can be even wider. This bandwidth is wide enough to process the signals of the next generation systems, opening up the possibility to realize a wide sampling receiver, which was not possible so for.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000538596
http://oasis.postech.ac.kr/handle/2014.oak/503
Article Type
Thesis
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