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Impact of High-k Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node

Title
Impact of High-k Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node
Authors
백록현홍재호이상현김예람정의영윤준식이정수정윤하
POSTECH Authors
백록현
Date Issued
8-Sep-2014
Publisher
The Japan Society of Applied Physics
URI
http://oasis.postech.ac.kr/handle/2014.oak/49464
Article Type
Conference
Citation
Solid State Devices and Materials (SSDM2014), 2014-09-08
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 BAEK, ROCK HYUN
Dept of Electrical Enginrg
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