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Issue Date	Title
2013-Apr	Effects of fin height of tapered FinFETs on the sub-22nm System on Chip (SoC) application using TCAD simulation IEEE VLSI-TSA (2013), 2013-04-22 백록현; 손창우; 강창용; 고명동; 박찬훈; 김성호; 정의영; 이정수; P.Kirsch; R.Jammy; J.C.Lee; 정윤하
2012-Apr	Comparative Study of Geometry-dependent Capacitances of Planar FETs and Double-Gate FinFETs: Optimization and Process Variation IEEE VLSI-TSA (2012), 2012-04-23 백록현; 손창우; 강창용; 최도영; 사공현철; 정의영; 이정수; P.Kirsch; R.Jammy; J.C.Lee; 정윤하
2012-Sep	Modeling and Analysis of the Parasitic Series Resistance in Raised Source/Drain FinFETs with Polygonal Shaped Epitaxy IEEE SISPAD 2012, 2012-09-05 백록현; 손창우; 강창용; P.Kirsch; R.Jammy; 고명동; 최도영; 사공현철; 정의영; 백창기; 이정수; 정윤하

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