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A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

Title
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
Authors
Kim, SHong, SChang, KJu, HShin, JKim, ByungsubPark, HJSim, JY
POSTECH Authors
Park, HJSim, JY
Date Issued
Feb-2016
Publisher
IEEE
Abstract
This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of 0.047 mm(2) and achieves a stable in-band phase noise of lower than -100 dBc/Hz in a wide range of supply voltage from 1 to 1.4 V.
Keywords
All-digital; frequency synthesizer; fractional-N; phase-locked loop; standard cell; synthesis; time-to-digital converter (TDC)
URI
http://oasis.postech.ac.kr/handle/2014.oak/37182
DOI
10.1109/JSSC.2015.2494365
ISSN
0018-9200
Article Type
Article
Citation
IEEE Journal of Solid-State Circuits, vol. 51, no. 2, page. 391 - 400, 2016-02
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 PARK, HONG JUNE
Dept of Electrical Enginrg
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