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Cited 9 time in webofscience Cited 6 time in scopus
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Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures

Title
Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures
Authors
OH, HYEON GWANKIM, JUNGSIKLEE, JUNYOUNGRIM, TAIUKBaek, CKLEE, JEONG SOO
Date Issued
Jan-2016
Publisher
ELSEVIER SCIENCE BV
Abstract
Effects of single grain boundary (SGB) and random interface traps (RITs) on the electrical characteristics of the macaroni structure in sub-30 nm poly-silicon (poly-Si) channel devices are analyzed using 3D simulation. The macaroni structure can mitigate the adverse effects of SGB on the electrical variations compared to the conventional structure. However, when RITs are considered at the interface between the dielectric filler and the poly-Si channel, the macaroni structures show relatively larger variations due to RITs at the inherent interface, compared with the conventional devices. Thus the reduction of interface traps in the macaroni devices is critical for sub-30 nm poly-Si device applications. (C) 2015 Elsevier B.V. All rights reserved.
URI
http://oasis.postech.ac.kr/handle/2014.oak/36141
ISSN
0167-9317
Article Type
Article
Citation
MICROELECTRONIC ENGINEERING, vol. 149, page. 113 - 116, 2016-01
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 LEE, JEONG SOO
Dept of Electrical Enginrg
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