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A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

Title
A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling
Authors
Bae, SJChi, HJSohn, YSLee, JSSim, JYPark, HJ
POSTECH Authors
Sim, JY
Date Issued
Aug-2009
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Abstract
A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25-mu m CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 x 120 mu m(2) and 10 mW, respectively, at the data rate of 2 Gb/s.
Keywords
Decision-feedback equalization (DFE); DRAM interface; equalizer; integration; intersymbol interference (ISI); multidrop bus; single-ended signaling; stubless channel; DECISION-FEEDBACK EQUALIZER; LOW-POWER; SERIAL LINK; DDR3 SDRAM; INTERFACE; DRAM; TRANSCEIVER; BACKPLANE; SCHEME; BUS
URI
http://oasis.postech.ac.kr/handle/2014.oak/26103
DOI
10.1109/TCSI.2008.2010099
ISSN
1549-8328
Article Type
Article
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 56, no. 8, page. 1645 - 1656, 2009-08
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 SIM, JAE YOON
Dept of Electrical Enginrg
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