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비이진 LDPC 부호를 위한 낮은 복잡도의 복호 방법 및 인터리버 설계

Title
비이진 LDPC 부호를 위한 낮은 복잡도의 복호 방법 및 인터리버 설계
Authors
김경범
Date Issued
2014
Publisher
포항공과대학교
Abstract
Low density parity-check (LDPC) codes have been shown to approach the Shannon-limit performance when the code length goes to infinify. On the other hand, for moderate code lengths, the error performance can be farther improved by constructing LDPC codes over finite fleld fields GF(q). However, this improvement is achieved at the expense of increased decoding complexity. In this thesis, we consider the problem of decoding nonbinary LDPC codes over GF(q) with reasonable complexity and good error-rate performance. First, the decoding algorithm with low complexity for nonbinary LDPC codes is proposed, named the weighted symbol reliablity algorithm (WSR) which uses syndrome checking result for measuring reliability of symbol nodes. Second, we analyze the extended min-sum (EMS) algorithm proposed by Declearq and Fossorier. These two approaches provide an effective trade-off between decoding complexity and error-performance, compared with the existing decoding algorithms. We also consider nonbinary LDPC codes conbined with high order QAM in order to apply them to realistic communication systems.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001674855
http://oasis.postech.ac.kr/handle/2014.oak/2120
Article Type
Thesis
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