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A Study on CMOS Power Amplifier for Wireless communication

Title
A Study on CMOS Power Amplifier for Wireless communication
Authors
Zhao, Chenxi
Date Issued
2014
Publisher
포항공과대학교
Abstract
As modern wireless communication technology evolves, RF power amplifiers (PAs) becomes a hot issue, because they are the key component of wireless mobile communication systems and the communication quality strongly depends on performance of the RF PAs. Modern wireless communication systems such as CDMA2000, WCDMA, OFDM, and so on, are intended to maximize data rate in a fast moving environment. The modulated signals of these systems require both good linearity and efficiency while the signals have a high peak to average power ratio. So the linearity and efficiency are two the most important characteristics of PAs for wireless applications. Recently, increasing numbers of RF components are being integrated using the CMOS process to meet the requirements of low cost and small size in wireless consumer markets. However, the CMOS power amplifier is difficult to design because of the low breakdown voltage, conductive Si substrate and lack of ground via. All make design of a full-integrated PA extremely challenging.This thesis focuses on efficiency enhancement and linearization techniques for CMOS power amplifiers design. Firstly, the basic design issues and approaches about bulk CMOS PA designs are introduced such as parameters optimization of power cell, layout of power cell, analysis of transformer and so on. Some bulk power cell solutions and transformer structure are given finally. Secondly, series combining transformer-based CMOS Doherty PA design method is studied. This Doherty PA uses a series combining transformer to combine the output voltage and realize the load modulation which is different from conventional current combining Doherty amplifiers. The prototype has a power-added efficiency (PAE) of 35 % at a maximum output power of 27.55 dBm from 3.4 V supply voltage. The PAE at 6 dB back-off is still high, about 30 %. It shows clearly the efficiency enhancement at the power back-off point due to the Doherty operation. This is the first use of voltage combining techniques in CMOS Doherty PA design. Finally, the Silicon-on-Insulator (SOI) CMOS process is described and a class-F PA is designed for GSM-high band application using 0.13-μm SOI process. Design, layout, and parasitic modeling considerations to attain high- efficiency PA operation are discussed. The simulation results show a good efficiency and linearity.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001673688
http://oasis.postech.ac.kr/handle/2014.oak/2063
Article Type
Thesis
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