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VLSI 설계에서 효율적인 크로스톡 타이밍 문제 검증에 대한 연구

VLSI 설계에서 효율적인 크로스톡 타이밍 문제 검증에 대한 연구
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With the continuous scaling down of process technology, crosstalk noise has become a main problem of recent VLSI systems. Because the space between devices shrinks continuously, coupling capacitance of the adjacent interconnect wires has increased. In other words, shrinking geometry decreases self-capacitance which is a net capacitance measured on driver and increases coupling capacitance which is a capacitance between adjacent wires. Moreover, voltage margin is continuously decreased due to low supply voltage for low-power design. These make the effect of crosstalk noise more severe. Crosstalk noise is an undesired noise from aggressor net to victim net when aggressor net changes the voltage value, and the crosstalk noise onto victim net affects the timing behavior of the victim signal. Due to increase of coupling capacitance, aggressor induces large amount of noise on victim. If we do not consider crosstalk noise during circuit design, it may cause switching and timing failure on IC chips. Therefore, it is necessary to accurately analyze crosstalk failure during design verification.Crosstalk failure can be divided with crosstalk switching failure and crosstalk timing failure. First, crosstalk switching failure occurs when victim has constant value. Because aggressor makes glitch on the victim, victim state can be switched. This failure called crosstalk switching failure. Second, crosstalk timing failure occurs when victim is switching state. Because aggressor affects victim, victim switching transition can be faster or slower. This failure called crosstalk timing failure.To analyze crosstalk failure accurately and efficiently, several methods for detecting crosstalk switching failure have been proposed. These methods compare glitch of victim receiver input or output with voltage value constraints or sensitivity, and detect glitch characteristics which cause crosstalk switching failure. However, current researches on crosstalk failure methods are mostly focused on crosstalk switching failure. Moreover, to detect crosstalk timing failure, conventional method requires victim receiver output simulation data, and have to compare victim receiver delay with timing constraints one by one.This thesis presents efficient method for detecting crosstalk timing failure. The proposed method does not require simulation data of victim receiver output and considers voltage characteristics of aggressor driver only.In this theses, the proposed method uses output charge values based on cumulative gate overdrive voltage (CGOV) method to detect crosstalk timing failure. When the aggressor switching time and slew rate, and timing constraints are given, the proposed method efficiently distinguishes crosstalk timing failure or not without simulations.The experiment was performed to examine the accuracy and efficiency of proposed method. In the experiments results, the proposed method shows 92.4% ‘Positive-True’ rate and 96.8% ‘Negative-False’ rate compared with HSPICE data, and reduced a CPU time of SPICE simulation by up to 91%.
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