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Recess Channel Array Transistor에서 발생하는 Mechanical Stress의 추출 방법 및 Nanoscale MOSFETs의 신뢰성에 대한 연구

Recess Channel Array Transistor에서 발생하는 Mechanical Stress의 추출 방법 및 Nanoscale MOSFETs의 신뢰성에 대한 연구
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This dissertation investigates the extraction method of mechanical stress induced by hybrid shallow-trench-isolation (STI) for dynamic random access memories (DRAMs) using recess channel array transistor (RCAT) structure and the reliability in nanoscale MOSFETs. The extraction method of mechanical stress is proposed, and assessments of the reliability for nanoscale MOSFETs are described in detail. For the RCAT-structure DRAM, the hybrid STI fabricated using high-density-plasma chemical-vapor-deposition (HDP-CVD) and spin-on-glass (SOG) processes was used to separate each cell in DRAMs. The hybrid STI induces both compressive and tensile stresses, so the extraction method for each stress is needed. The mechanical stress at the channel region was evaluated using the subthreshold current method, and mechanical stress at the drain region was evaluated using the gate induced drain leakage current IGIDL method. Experimental results indicate that a biaxial tensile stress in the range of 70.26-399.2 MPa was induced by the SOG bottom layer, while a biaxial compressive stress in the range of 0.220-7.291 GPa was induced by the HDP-CVD SiO2 top layer. In addition, the mechanical stress varied the data retention time tret by ~67.1%. tret had a strong correlation with the biaxial tensile stress, but had little correlation with the biaxial compressive stress. For a nanoscale nMOSFET, electron-electron scattering (EES) rate increases with scaling down of MOSFETs, so the effect of EES on a device life time is investigated. Experimental results indicate that EES stress creates more interface states and negative oxide charges than does channel hot-carrier (CHC) stress. IGIDL and substrate current were measured to investigate the uniformity of the damage. They confirm that defects generated by EES are distributed in the channel and drain region, whereas CHC stress caused the damage at the drain region. The life time under EES stress was shorter than that under CHC stress. Thus, EES stress should be considered as the worst case hot carrier stress condition. In addition, high-k/metal gate p-channel FET under a low stress voltage of negative bias temperature instability (NBTI) degradation is investigated. High-k metal gate stacks are used to block the direct tunneling of carriers through the gate oxide. However, the trapping and de-trapping of electrons and holes induces serious NBTI problems. Especially, the turn-around effect occurs when NBTI stresses are applied. Thus, the mechanism of NBTI degradation and the turn-around effect should be investigated. Direct current-current voltage and carrier separation methods are used to separate the effect of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges to degrade the device, but a low stress voltage generates negative oxide charges which induces the turn-around effect of the threshold voltage. This experimental observation suggests that the turn-around effect should be considered when evaluating the device reliability. These experimental observations suggest that the effect of mechanical stresses and reliability problems such as EES, NBTI increase with the scaling down of MOSFETs. Thus mechanical stresses, EES, NBTI should be seriously considered while evaluating the reliability of nanoscale MOSFETs.
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